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Boolean Logic Truth Table Generator

Dynamically generate complete 8-row truth tables for 3-variable logic circuits across AND, OR, XOR, NAND, and NOR gates. Includes De Morgan's laws, NAND/NOR universality, transistor counts, operator precedence, and circuit simplification guidance.
Runtime Equation Matrix
Q = (A AND B) OR C
Output \u2261 (A & B) | C
Input AInput BInput COutput (Q)
0000
0011
0100
0111
1000
1011
1101
1111

Universal Logic Gates

NAND and NOR are known as "Universal Gates." Because of their strict inverted logic, you can physically construct every other type of gate (AND, OR, NOT) simply by chaining NAND or NOR gates together. Early Apollo guidance computers were forged almost entirely using massive blocks of identical NOR gates to reduce complexity and component failure vectors.

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What is Boolean Logic: Gate Architecture, De Morgan's Laws & Universal Gates?

Every computation ever performed by a digital device — from a 1970s pocket calculator to a modern GPU running machine learning — reduces to combinations of six fundamental logic gates: AND, OR, NOT, NAND, NOR, and XOR. These gates evaluate binary (0 or 1) inputs according to precise mathematical rules derived from George Boole's 1847 algebraic system. In hardware, they are implemented as networks of transistors acting as voltage-controlled switches: a CMOS 2-input NAND gate uses just 4 transistors; a modern CPU contains billions. Understanding gate behavior, De Morgan's transformations, and the universality of NAND and NOR gates is foundational to digital logic design, FPGA programming, CPU architecture, and compiler optimization.

Mathematical Foundation

NAND (Universal Gate) — Any Logic Implemented with NAND Alone
Q=¬(A∧B)=A⋅B‾Q = \neg (A \land B) = \overline{A \cdot B}
¬/  ‾\neg / \overline{\;}= Logical NOT (inversion). Flips 0 to 1 and 1 to 0. In hardware: implemented by a single transistor (CMOS: one PMOS + one NMOS). NAND output = 0 ONLY when both A=1 AND B=1. All other input combinations produce output=1.
∧/⋅\land / \cdot= Logical AND. Output=1 ONLY when ALL inputs are 1. In CMOS hardware: 2 NMOS transistors in series (pull-down network) + 2 PMOS in parallel (pull-up network) = 4 transistors per 2-input NAND gate. AND requires an extra inverter = 6 transistors.
Universality\text{Universality}= NAND alone can implement NOT (A NAND A), AND (NAND + inverter), OR (De Morgan: NOT-A NAND NOT-B = A OR B), and NOR (invert OR output). This is why NAND is called a universal gate — any digital circuit can be built using only NAND gates.
NOR (Universal Gate) — De Morgan's Dual of NAND
Q=¬(A∨B)=A+B‾Q = \neg (A \lor B) = \overline{A + B}
∨/+\lor / += Logical OR. Output=1 when AT LEAST ONE input is 1. Output=0 ONLY when all inputs are 0.
De Morgansˊ Law\text{De Morgan\'s Law}= \overline{A \cdot B} = \overline{A} + \overline{B} (NAND = OR of NOTs). The dual: \overline{A + B} = \overline{A} \cdot \overline{B} (NOR = AND of NOTs). De Morgan's laws are the key to converting between NAND-based and NOR-based circuit implementations and to simplifying Boolean expressions.
XOR (Exclusive OR) — Fundamental to Binary Arithmetic
Q=A⊕B=(A∧¬B)∨(¬A∧B)Q = A \oplus B = (A \land \neg B) \lor (\neg A \land B)
⊕\oplus= XOR operator. Output=1 when inputs DIFFER (0,1 or 1,0). Output=0 when inputs MATCH (0,0 or 1,1). XOR is the core of half-adder circuits: the sum bit of 1+1 in binary is 0 (XOR output) with carry=1 (AND output). A full adder uses two XOR gates + two AND gates + one OR gate to add three bits.

Laws & Principles

  • De Morgan's laws (the two duality theorems of Boolean algebra): (1) NOT(A AND B) = (NOT A) OR (NOT B). Equivalently: A NAND B = (NOT A) OR (NOT B). (2) NOT(A OR B) = (NOT A) AND (NOT B). Equivalently: A NOR B = (NOT A) AND (NOT B). These laws are essential for circuit simplification: converting AND-OR logic to all-NAND or all-NOR implementations, which reduces transistor count and propagation delay in real circuits. Verification: A=1, B=0. NOT(1 AND 0) = NOT(0) = 1. (NOT 1) OR (NOT 0) = 0 OR 1 = 1. ✓
  • NAND universality — building all gates from NAND alone: NOT(A) = A NAND A (both inputs tied together). AND(A,B) = NOT(A NAND B) = (A NAND B) NAND (A NAND B). OR(A,B) = (NOT A) NAND (NOT B) = (A NAND A) NAND (B NAND B). This universality is exploited in industrial chip design: standardized NAND cell libraries allow automated synthesis tools to implement any Boolean function using a single, well-characterized gate type, minimizing design complexity and manufacturing variability. 74xx TTL NAND gates (7400) and their CMOS equivalents (4011) are among the most manufactured electronic components in history.
  • Operator precedence in Boolean algebra (highest to lowest): (1) Parentheses — always evaluated first. (2) NOT — applied to the immediately following variable or parenthesized expression. (3) AND (logical multiplication) — evaluated before OR. (4) OR (logical addition) — lowest precedence. Example: A OR B AND C ≡ A OR (B AND C), NOT A OR B ≡ (NOT A) OR B (NOT does NOT bind the whole expression). This mirrors algebraic precedence: multiplication before addition, which is why Boolean expressions use · for AND and + for OR.
  • XOR and binary arithmetic: XOR is the mathematical foundation of binary addition. Sum bit = A XOR B. Carry bit = A AND B (half adder). Full adder (3 inputs: A, B, C_in): Sum = A XOR B XOR C_in; Carry_out = (A AND B) OR (C_in AND (A XOR B)). An 8-bit ripple-carry adder chains 8 full adders. XOR is also self-inverse: A XOR A = 0, A XOR 0 = A. This makes XOR the core operation in symmetric encryption ciphers (AES, ChaCha20), RAID-5/6 parity calculations, error-correcting codes (Hamming, CRC), and pseudo-random number generators (LFSRs).

Step-by-Step Example Walkthrough

" Evaluate the 3-variable expression Q = (A NAND B) XOR C, then apply De Morgan's law to show the NAND-free equivalent. Given A=1, B=1, C=0. "

  1. Resolve NAND: A NAND B = NOT(1 AND 1) = NOT(1) = 0
  2. Apply XOR: Q = 0 XOR C = 0 XOR 0 = 0
  3. De Morgan equivalent: A NAND B ≡ (NOT A) OR (NOT B) = (NOT 1) OR (NOT 1) = 0 OR 0 = 0 ✓
  4. Verify XOR with equivalent: 0 XOR 0 = 0 ✓
  5. Full truth row: A=1, B=1, C=0 → NAND(A,B)=0, XOR(0,C)=0 → Q=0
Final Result: Q = 0 for A=1, B=1, C=0. De Morgan's law confirms the NAND result independently: (NOT A) OR (NOT B) = 0 = the NAND output, validating both the gate evaluation and the algebraic equivalence.

Quick Answer: What does each Boolean logic gate do?

AND: output=1 only when ALL inputs=1. OR: output=1 when ANY input=1. NOT: inverts the input (0→1, 1→0). NAND: NOT(AND) — output=0 only when ALL inputs=1; all others output=1. NOR: NOT(OR) — output=1 only when ALL inputs=0. XOR: output=1 when inputs are DIFFERENT, 0 when SAME. De Morgan: NOT(A AND B) = (NOT A) OR (NOT B); NOT(A OR B) = (NOT A) AND (NOT B). NAND and NOR are universal gates — any logic circuit can be built from NAND alone or NOR alone. XOR is the sum bit in binary addition (AND is the carry bit).

Complete Gate Truth Table: All 6 Fundamental Boolean Gates

Truth tables are exhaustive: they enumerate every possible input combination and its output. For 2 inputs (A, B), there are 2² = 4 rows. The calculator above generates 2³ = 8 rows for 3 variables. XNOR (not shown) is the complement of XOR: output=1 when inputs MATCH.

A B AND (A·B) OR (A+B) NAND NOR XOR (A⊕B) NOT A
00001101
01011011
10011010
11110000
Pattern count:1 HIGH3 HIGH3 HIGH1 HIGH2 HIGH2 HIGH
CMOS transistors:664 ← minimum4 ← minimum~102

Pro Tips & Common Boolean Logic Mistakes

Do This

  • ✓Apply De Morgan’s laws to convert AND-OR expressions to all-NAND implementations for hardware efficiency. System-on-chip (SoC) and FPGA designs typically use standard cell libraries where NAND and NOR gates have the smallest transistor footprint (4 transistors for a 2-input gate vs. 6 for AND and OR). Automated synthesis tools (Synopsys Design Compiler, Cadence Genus) apply De Morgan’s transformations automatically, but understanding the rules lets you pre-optimize expressions before synthesis: NOT(A AND B AND C) = (NOT A) OR (NOT B) OR (NOT C). A 3-input NAND uses 6 transistors; the AND-NOT equivalent is 6+2=8 transistors. At millions of gates, this difference compounds significantly into die area, power consumption, and timing closure.
  • ✓Use XOR’s self-inverse property (A XOR A = 0, A XOR 0 = A) when debugging encryption, parity, and checksum implementations. XOR encryption works because XOR is its own inverse: (plaintext XOR key) XOR key = plaintext. If you encrypt with XOR and decryption gives garbage, the first thing to verify is whether the key is identical in both operations (byte-for-byte, length-for-length). RAID-5 parity: parity block = D0 XOR D1 XOR D2. Recovery: D0 = parity XOR D1 XOR D2. CRC checksums: the remainder of polynomial long division where XOR replaces subtraction. In all these applications, the commutativity (A XOR B = B XOR A) and associativity ((A XOR B) XOR C = A XOR (B XOR C)) properties of XOR are relied upon implicitly.

Avoid This

  • ✗Don't confuse XOR with OR in software conditionals — they have different output patterns on the 1,1 input case. OR(1,1) = 1. XOR(1,1) = 0. In most programming languages, the bitwise XOR operator is ^ and bitwise OR is |. The logical OR is ||. These are all different: 1 | 1 = 1, 1 ^ 1 = 0, 1 || 1 = true. A common bug in access control logic: using || (OR) when the intent is “exactly one of these conditions, not both” (which requires XOR). Example: if (is_admin || is_editor) allows a user who is both admin AND editor, possibly creating privilege escalation. If the intent is “one or the other but not both,” the correct logic is XOR, which must be manually implemented in most languages as (a || b) && !(a && b).
  • ✗Don't apply De Morgan’s law partially — the inversion must apply to BOTH the operator AND all operands simultaneously. Incorrect: NOT(A AND B) = (NOT A) AND (NOT B). This is wrong — the AND was not flipped to OR. Correct: NOT(A AND B) = (NOT A) OR (NOT B). The complete De Morgan transformation has two steps: (1) invert the entire expression, (2) flip the operator (AND↔OR) AND invert each variable. Both steps are mandatory. Partial application produces incorrect logic that will never be caught by a compiler — it is logically sound syntax with wrong semantics. Verify with any input: A=1, B=0. NOT(1 AND 0) = NOT(0) = 1. Incorrect: (NOT 1) AND (NOT 0) = 0 AND 1 = 0. Correct: (NOT 1) OR (NOT 0) = 0 OR 1 = 1. ✓

Frequently Asked Questions

Why are NAND and NOR called “universal gates”?

A universal gate is one from which ALL other Boolean functions can be constructed using only that gate type. NAND implementations: NOT(A) = A NAND A (tie both inputs). AND(A,B) = (A NAND B) NAND (A NAND B) (invert the NAND output). OR(A,B) = (A NAND A) NAND (B NAND B) (NAND of two NOTs, applying De Morgan). NOR(A,B) = invert OR, which is invert [(A NAND A) NAND (B NAND B)]. XOR requires 4 NAND gates in a specific feedback-free arrangement. Why does this matter? Chip designers can fabricate a single optimized NAND cell and implement any logic function by connecting multiple copies. The original 7400-series TTL chips (1960s) were quad 2-input NAND gates because of this universality. Modern FPGAs use lookup tables (LUTs) as configurable truth tables instead, but the NAND universality principle remains foundational to the logic synthesis software that maps designs onto FPGAs and ASICs.

What are De Morgan’s laws and how do you apply them?

De Morgan’s laws (1847) provide the two fundamental duality transformations of Boolean algebra: Law 1: NOT(A AND B) = (NOT A) OR (NOT B) — the complement of a product equals the sum of complements. Law 2: NOT(A OR B) = (NOT A) AND (NOT B) — the complement of a sum equals the product of complements. Application steps: (1) Invert (NOT) the entire expression. (2) Change AND to OR (or OR to AND). (3) Invert each individual variable. All three steps are required simultaneously. Example: Simplify NOT(NOT A AND NOT B): Apply Law 1 in reverse — this equals (NOT(NOT A)) OR (NOT(NOT B)) = A OR B. This is simply an OR gate — no NANDs needed. Practical use: NAND gate with inverted inputs = OR gate (De Morgan equivalent). NOR gate with inverted inputs = AND gate. These “DeMorgan equivalent” symbols are used on logic diagrams to show signal polarity clearly.

How does a truth table relate to real digital hardware?

A truth table is the precise behavioral specification of a logic gate or combinational circuit. In real CMOS hardware: Logic 1 (HIGH) ≈ supply voltage (1.8V–3.3V depending on process node). Logic 0 (LOW) ≈ 0V (ground). A 2-input NAND gate in 28nm CMOS: 4 transistors, gate propagation delay ~20–50 picoseconds, power consumption in the microwatt range per gate at 1 GHz. The truth table’s four rows correspond to four distinct voltage-state combinations on the two input pins. Silicon designers verify gate behavior against truth tables using SPICE circuit simulation before tape-out. At higher abstraction levels, hardware description languages (VHDL, Verilog, SystemVerilog) describe circuit behavior functionally — synthesis tools then map the behavioral description to standard cell gates by matching subexpressions to gate truth tables in the library. A 100 million gate design is ultimately just 2n-row truth tables applied recursively through a hierarchy.

What is Boolean simplification and why does it matter for circuit design?

Boolean simplification reduces a logic expression to a minimal form with fewer gates — directly translating to smaller die area, lower power, and faster propagation delay in physical circuits. Key identities: Idempotent: A AND A = A; A OR A = A. Complement: A AND (NOT A) = 0; A OR (NOT A) = 1. Absorption: A OR (A AND B) = A; A AND (A OR B) = A. Distribution: A AND (B OR C) = (A AND B) OR (A AND C). Karnaugh maps (K-maps) provide a visual method for simplification: group adjacent 1s (in powers of 2) in the truth table grid to identify shared factors. A 3-variable K-map handles 8 rows (the same 8 rows as this calculator’s output). For more than 6 variables, the Quine-McCluskey algorithm or SAT solvers are used algorithmically. Every modern synthesis tool performs Boolean simplification automatically, reducing gate count by 20–60% over unoptimized implementations.

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